MT29C1G12MAACVAMD-5 IT

Preliminary‡ 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Features NAND Flash and Mobile LPDRAM 152-Ball Package-on-Package (PoP) Combination Memory (TI OMAP™) MT29C Family Current production part numbers: See Table 1 on page 3 Features Figure 1: • Micron® NAND Flash and Mobile LPDRAM components • RoHS-compliant, “green” package • Separate NAND Flash and Mobile LPDRAM interfaces • Space-saving package-on-package combination • Low-voltage operation (1.70–1.95V) • Industrial temperature range: –40°C to +85°C PoP Block Diagram NAND Flash Power NAND Flash Device NAND Flash Interface LP-DRAM Device LP-DRAM Interface NAND Flash-Specific Features • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) LP-DRAM Power Mobile LPDRAM-Specific Features • • • • • • • • No external voltage reference required No minimum clock rate requirement 1.8V LVCMOS-compatible inputs Programmable burst lengths Partial-array self refresh (PASR) Deep power-down (DPD) mode Selectable output drive strength STATUS REGISTER READ (SRR) supported1 Options • LP-DRAM 166 MHz CL32 133 MHz CL3 Marking -6 -75 Notes: 1. Contact factory for remapped SRR output. 2. CL = CAS (READ) latency. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Part Numbering Information – 152-Ball PoP Part Numbering Information – 152-Ball PoP Micron NAND Flash and LPDRAM devices are available in different configurations and densities. Figure 2: 152-Ball Part Number Chart MT 29C 1G 24M A C J A CG –x IT ES Production Status Micron Technology Blank = Production Product Family ES = Engineering sample 29C = NAND + LPDRAM MCP MS = Mechanical sample NAND Density Operating Temperature Range 1G = 1Gb IT = Industrial (–40° to +85°C) 2G = 2Gb LPDRAM Self Refresh Current 4G = 4Gb Blank = Standard LPDRAM Density 12M = 512Mb 24M = 1024Mb LPDRAM Access Time 48M = 2048Mb –6 166 MHz CL3 –75 133 MHz CL3 Operating Voltage Range Package Codes A = 1.8V (1.70–1.95V) CA = 152-ball PoP VFBGA (14 x 14 x 0.9mm) CG = 152-ball PoP VFBGA (14 x 14 x 1.0mm) NAND Flash Configuration Width Density C x8 1Gb First D x16 1Gb First J x8 2Gb Second K x16 2Gb Second N x8 4Gb First P x16 4Gb JQ = 152-ball PoP TFBGA (14 x 14 x 1.1mm) Generation Chip Count First U x8 1Gb Second V x16 1Gb Second LPDRAM Configuration 1, 1 1 NAND, 1 DRAM 1Gb First B 1, 1 2 NAND, 1 DRAM x32 1Gb First C 1, 2 1 NAND, 2 DRAM DDR x16 512Mb Second D 1, 2 2 NAND, 2 DRAM DDR x32 512Mb Second Density J DDR x16 L DDR N R PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN Chip Count A Width Note: CE#, CS# Generation Type Not all possible combinations are available. Contact factory for availability. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Device Marking Table 1: Production Part Numbers Part Number MT29C4G48MAPLCCA-6 IT MT29C4G48MAPLCCA-75 IT MT29C4G48MAPLCJQ-6 IT MT29C4G48MAPLCJQ-75 IT MT29C1G12MADRACG-6 IT MT29C1G12MADRACG-75 IT MT29C2G24MAKLACG-6 IT MT29C2G24MAKLACG-75 IT MT29C1G12MAURACA-6 IT MT29C1G12MAURACA-75 IT MT29C1G12MAVRACA-6 IT MT29C1G12MAVRACA-75 IT NAND Product LPDDR Product Physical Part Marking MT46H32M32LFJG-6 IT MT46H32M32LFJG-6 IT MT46H32M32LFJG-6 IT MT46H32M32LFJG-6 IT MT46H16M32LFCM-6 IT MT46H16M32LFCM-6 IT MT46H32M32LFJG-6 IT MT46H32M32LFJG-6 IT MT46H16M32LFCM-6 IT MT46H16M32LFCM-6 IT MT46H16M32LFCM-6 IT MT46H16M32LFCM-6 IT MT29F4G16ABCWC-ET MT29F4G16ABCWC-ET MT29F4G16ABCWC-ET MT29F4G16ABCWC-ET MT29F1G16ABBHC-ET MT29F1G16ABBHC-ET MT29F2G16ABDHC-ET MT29F2G16ABDHC-ET MT29F1G08ABCHC-ET MT29F1G08ABCHC-ET MT29F1G16ABCHC-ET MT29F1G16ABCHC-ET JW399 JW400 JW297 JW296 JW226 JW227 JW188 JW189 JW385 JW384 JW375 JW374 Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP General Description General Description Micron package-on-package (PoP) products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low-power, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete memory products portfolio. The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses. The NAND Flash and Mobile LPDRAM devices have separate core power connections and share a common ground (i.e., VSS is tied together on the two devices). The bus architecture of this device also supports separate NAND Flash and Mobile LPDRAM functionality without concern for device interaction. Operational characteristics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron data sheets for each of the discrete devices. For device specifications and complete Micron NAND Flash features documentation, please refer to the component data sheet at www.micron.com/products/nand, or contact your local Micron sales office. For device specifications and complete Mobile LPDRAM features documentation, please refer to the component data sheet at www.micron.com/products/mobiledram, or contact your local Micron sales office. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16) 17 18 19 20 21 NC NC NC NC A NC NC NC B NC NC NC C NC NC NC NC D E NC NC NC NC E F VSSQ VDDQ VSSQ VDDQ F G NC NC A0 NC G H NC VSS VSS VDD H J VDD NC A2 A3 J K WE# NC A1 A9 K L NC RE# VDDQ VSSQ L M NC VSS A7 A6 M N NC VCC A8 A11 N P NC NC VSS VDD P R NC VSS A5 A12 R T NC VCC CS1# CS0# T U I/O1 I/O0 CAS# A4 U V I/O3 I/O2 BA1 RAS# V W CE1# LOCK VSSQ VDDQ W Y NC NC I/O6 I/O7 WP# VSS VCC NC NC R/B# VSS A14 CKE1 VDD CKE0 A10 VSS WE# VSSQ NC NC Y AA NC NC I/O4 I/O5 NC VCC VSS CE0# ALE CLE VDD TQ VSS VDDQ A13 VSSQ VDD BA0 VDDQ NC NC AA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A NC NC VDDQ LDM DQ5 DQ7 VSSQ DQ2 DQ4 DQ8 DQ11 CK VSS UDM B NC NC NC NC VDDQ DQ1 DQ6 LDQS DQ3 DQ0 DQ9 DQ10 CK# VSSQ UDQS C VSSQ D Top View – Ball Down Note: PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 15 16 VDDQ DQ13 DQ12 NAND VDD DQ15 DQ14 LPDDR Supply Ground Contact factory for availability of x16 LPDDR configuration. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Ball Assignments and Descriptions Figure 4: 152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32) 6 7 8 9 10 11 17 20 21 VDDQ DQ21 DQ20 DM3 DQS3 NC NC A DQ23 DQ22 DQ28 NC NC B 12 13 14 15 CK VSS DM2 CK# VSSQ DQS2 18 19 1 2 3 A NC NC VDDQ DM1 DQ13 DQ15 B NC NC DQ6 DQ7 C VSSQ DQS0 DQ24 DQ26 C D DQ3 DQ5 DQ25 DQ29 D E DQ0 DQ1 DQ27 DQ31 E F VSSQ VDDQ VSSQ VDDQ F G DQ4 DQ2 A0 DQ30 G H DM0 VSS VSS VDD H J VDD I/O14 A2 A3 J K WE# I/O15 A1 A9 K L NC RE# VDDQ VSSQ L M I/O13 VSS A7 A6 M N I/O10 VCC A8 A11 N P I/O12 I/O11 VSS VDD P R I/O8 VSS A5 A12 R T I/O9 VCC CS1# CS0# T U I/O1 I/O0 CAS# A4 U V I/O3 I/O2 BA1 RAS# V W CE1# LOCK VSSQ VDDQ W Y NC NC I/O6 I/O7 WP# VSS VCC NC NC R/B# VSS RFU CKE1 VDD CKE0 A10 VSS WE# VSSQ NC NC Y AA NC NC I/O4 I/O5 NC VCC VSS CE0# ALE CLE VDD TQ VSS VDDQ A13 VSSQ VDD BA0 VDDQ NC NC AA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 4 5 VDDQ DQ9 VSSQ DQ10 DQ12 DQ16 DQ19 DQ14 DQS1 DQ11 DQ8 DQ17 DQ18 Top View (Ball Down) PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 6 NAND 16 VDD LP-DRAM Supply Ground Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Ball Assignments and Descriptions Table 2: x8/x16 NAND Ball Descriptions Symbol Type ALE Input CE1#, CE0# CLE Input Input LOCK Input RE# WE# WP# I/O[7:0] (x8) Input Input Input Input/ output I/O[15:0] (x16) R/B# Output VCC Supply Description Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address register. Chip enable: Gates transfers between the host system and the NAND Flash device. Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip command register. When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down). Read enable: Gates information from the NAND device to the host system. Write enable: Gates information from the host system to the NAND device. Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations. Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs. I/O[15:8] are RFU1 for NAND x8 devices. Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress. VCC: NAND power supply. Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact the factory for details. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Ball Assignments and Descriptions Table 3: x16/x32 LPDDR Ball Descriptions Symbol Type A[14:0] Input BA1, BA0 CAS# CK, CK# Input Input Input CKE0, CKE1 Input CS1#, CS0# Input LDM, UDM (x16) Input Description Address inputs: Specifies the row or column address. Also used to load the mode registers. The maximum LPDDR address is determined by density and configuration. Consult the LPDDR product data sheet for the maximum address for a given density and configuration. Unused address pins become RFU. Bank address inputs: Specifies one of the 4 banks. Column select: Specifies the command to execute. CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#. Clock enable: CKE0 is used for a single LPDDR product. CKE1 is used for dual LPDDR products. Chip select: CS0# is used for a single LPDDR product. CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. Data mask: Determines which bytes are written during WRITE operations. For x16 LPDDR, unused DM balls become RFU. DM[3:0] (x32) RAS# WE# DQ[15:0] (x16) Input Input Input/ output Row select: Specifies the command to execute. Write enable: Specifies the command to execute. Data bus: Data inputs/outputs. DQ[31:16] are RFU for x16 LPDDR devices. DQ[31:0] (x32) LDQS, UDQS (x16) Input/ output Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte. For x16 LPDDR, unused DQS balls become RFU. DQS[3:0] (x32) TQ VDD VDDQ VSSQ Output Supply Supply Supply Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C. VDD: LPDDR power supply. VDDQ: LPDDR I/O power supply. VSSQ: LPDDR I/O ground. Table 4: Symbol VSS NC RFU1 Non-Device-Specific Ball Descriptions Type Supply – – Description VSS: Shared ground. No connect: Not internally connected. Reserved for future use. Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact the factory for details. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Electrical Specifications Electrical Specifications Table 5: Absolute Maximum Ratings Parameters/Conditions Symbol Min Max Unit VCC, VDD, VDDQ Supply voltage relative to VSS Voltage on any pin relative to VSS Storage temperature range VCC, VDD, VDDQ VIN –1.0 2.4 V –0.5 V – –55 2.4 or (supply voltage1 + 0.3V), whichever is less +150 °C Notes: 1. Supply voltage references either VCC,VDD, or VDDQ. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6: Recommended Operating Conditions Parameters Symbol Min Typ Max Unit Supply voltage I/O supply voltage Operating temperature range VCC, VDD VDDQ – 1.70 1.70 –40 1.80 1.80 – 1.95 1.95 +85 V V °C PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Device Diagrams Device Diagrams Figure 5: 152-Ball Functional Block Diagram (Single LPDDR) CE0# VCC CLE ALE NAND Flash RE# I/O WE# WP# R/B# LOCK VSS CS0# VDD CK VDDQ CK# DM LPDDR CKE0 RAS# DQ CAS# WE# DQS TQ Address, VSSQ BA0, BA1 PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Device Diagrams Figure 6: 152-Ball Functional Block Diagram (Dual LPDDR) CE0# VCC CLE ALE NAND Flash RE# I/O WE# WP# R/B# VSS CS0#, CS1# VDD CK VDDQ CKE0, CKE1 DQM RAS# LPDDR CAS# (Die 0 and 1) DQ WE# TQ PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN Address, VSS BA0, BA1 VSSQ 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Package Dimensions Package Dimensions Figure 7: 152-Ball VFBGA (Package Code: CA) 0.46 ±0.1 Seating plane A 0.12 A 152X Ø0.45 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 14 ±0.1 Ball A1 ID Ball A1 ID 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K 13 14 ±0.1 CTR L M N P R T U V W 0.65 TYP Y AA 0.65 TYP 0.9 MAX 0.35 MIN 13 CTR Note: PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN All dimensions are in millimeters. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Package Dimensions Figure 8: 152-Ball VFBGA (Package Code: CG) Seating plane A 0.6 ±0.1 0.1 A 152X Ø0.46 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. Ball A1 ID 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D Ball A1 ID E F G H J K L 13 CTR 14 ±0.1 M N P R T U V W 0.65 TYP Y AA 1.0 MAX 0.65 TYP 0.35 MIN 13 CTR 14 ±0.1 Note: PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN All dimensions are in millimeters. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Package Dimensions Figure 9: 152-Ball TFBGA (Package Code: JQ) Seating plane A 0.75 ±0.1 0.12 A 152X Ø0.45 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. Ball A1 ID 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Ball A1 ID 13 CTR 0.65 TYP A B C D E F G H J K L M N P Q R T U V W X 14 ±0.1 1.1 MAX 0.65 TYP 0.35 MIN 13 CTR 14 ±0.1 Notes: 1. All dimensions are in millimeters. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP Revision History Revision History Rev. E, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/09 • “NAND Flash-Specific Features” on page 1: Deleted device size bullet. • Figure 2: “152-Ball Part Number Chart,” on page 2: Added U and V options under NAND Flash configurations; deleted low-power option under LPDRAM self refresh current; added dimensions to package codes; added CS# to first column under chip count; changed CE# from 2 to 1 for B and D under chip count. • Table 1, “Production Part Numbers,” on page 3: Replaced former table 1. • Figure 3: “152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16),” on page 5: Updated figure. • Figure 4: “152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32),” on page 6: Updated figure. • Table 2, “x8/x16 NAND Ball Descriptions,” on page 7: Updated table. • Table 3, “x16/x32 LPDDR Ball Descriptions,” on page 8: Updated table. • Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Updated table. • Table 5, “Absolute Maximum Ratings,” on page 9: Updated table. • Table 6, “Recommended Operating Conditions,” on page 9: Updated table. • Figure 5: “152-Ball Functional Block Diagram (Single LPDDR),” on page 10: Updated figure title; updated figure. • Figure 6: “152-Ball Functional Block Diagram (Dual LPDDR),” on page 11: Added figure. Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/08 • Updated template; ready for external publication. Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08 • Added part number for JQ package code, page 1. • Figure 2, Marketing Part Number Example, on page 2: added JQ package code. • Added JQ package diagram, Figure 9, 152-Ball TFBGA (Package Code: JQ), on page 14. Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 • • • • On page 1, added part number for CA package code. Figure 2: Marketing Part Number Example on page 2: Added CA package code. Removed former capacitance tables. See component data sheets for capacitance. Figure 7: 152-Ball VFBGA (Package Code: CA) on page 12, and Figure 8: 152-Ball VFBGA (Package Code: CG) on page 13: Updated figures. Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08 • Initial release. PDF: 09005aef8326e5ac / Source: 09005aef8326e59a 152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved.